CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW FIFO CACHE
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
Sep 8, 2016
app pub date -
Dec 12, 2014
filing date -
Oct 8, 2014
priority date (Note) -
Published
status (Latency Note)
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Importance

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Abstract
A cache memory system including a primary cache and an overflow cache that are searched together using a search address. The overflow cache operates as an eviction array for the primary cache. The primary cache is addressed using bits of the search address, and the overflow cache is configured as a FIFO buffer. The cache memory system may be used to implement a translation lookaside buffer for a microprocessor.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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VIA ALLIANCE SEMICONDUCTOR CO LTD | SHANGHAI 201203 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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EDDY, COLIN | Austin, US | 78 | 887 |
# of filed Patents : 78 Total Citations : 887 | |||
HOOKER, RODNEY E | Austin, US | 140 | 2878 |
# of filed Patents : 140 Total Citations : 2878 |
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Patent Citation Ranking
- 7 Citation Count
- G06F Class
- 11.69 % this patent is cited more than
- 9 Age
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Mar 8, 2028 |
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