APPARATUS FOR CALIBRATING OFF-CHIP DRIVER/ON-DIE TERMINATION CIRCUITS
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United States of America Patent
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Issued Date -
Sep 1, 2016
app pub date -
Feb 26, 2015
filing date -
Feb 26, 2015
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An impedance calibration circuit is provided for off-chip driver/on-die termination circuits. The impedance calibration circuit includes a first circuit that includes first PMOS transistors coupled in parallel between a power supply terminal and a first output terminal, second PMOS transistors coupled in parallel between the power supply terminal and a second output terminal, first NMOS transistors coupled in parallel between the second output terminal and a GROUND terminal, a third PMOS transistor coupled in parallel with the first PMOS transistors between a power supply terminal and a first output terminal, and a second NMOS transistor coupled in parallel with the first NMOS transistors between the second output terminal and a GROUND terminal.
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