PLL circuit and control method thereof
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United States of America Patent
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Jan 24, 2017
Grant Date -
Aug 25, 2016
app pub date -
Dec 7, 2015
filing date -
Feb 19, 2015
priority date (Note) -
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Abstract
According to one embodiment, a PLL circuit includes: a phase comparator (13); a pulse width control unit that adjusts a pulse width of comparison results (UP, DN) of the phase comparator (13) and outputs comparison results (UPi, DNi) having a pulse width smaller than that of comparison results (UPp, DNp); a charge pump (14) that outputs a current (Ip) according to the comparison results (UPp, DNp); a charge pump (15) that outputs a current (Ii) according to the comparison results (UPi, DNi); a filter (16) that removes a high-frequency component of a voltage generated based on the current (Ip) and outputs a control voltage (Vp); a filter (17) that outputs, as a control voltage (Vi), a result obtained by integrating the current (Ii); and a voltage control oscillator (18) that generates an oscillating signal having a frequency according to the control voltage (Vp, Vi).
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