SEMICONDUCTOR TEMPLATE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Aug 25, 2016
app pub date -
Feb 19, 2015
filing date -
Feb 19, 2015
priority date (Note) -
Abandoned
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Abstract
The present invention provides a semiconductor template, comprising: a substrate; a buffer layer, disposed on a surface of the substrate and comprises a first sub-buffer layer and a second sub-buffer layer sequentially stacked, wherein the buffer layer has irregular cracks such that the top surface of the buffer layer is discontinuous, and the depth of the cracks are greater than or equal to the thickness of the second sub-buffer layer and less than or equal to sum of the thickness of the first sub-buffer and the second sub-buffer layer; and an epitaxial layer, which is a continuous layer and disposed on the buffer layer.
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