CHIP PACKAGING STRCUTRE AND MANUFATURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Aug 25, 2016
app pub date -
Jun 5, 2015
filing date -
Feb 25, 2015
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Abstract
A chip packaging structure including a substrate, at least one chip, a plurality of conductive bumps, and an electrically insulating and thermally conductive material is introduced. The chip is disposed on a chip carrier, and the chip carrier is disposed on the substrate. The conductive bumps are disposed between the substrate and the chip carrier to electrically connect the substrate and the chip. The electrically insulating and thermally conductive material is disposed around and between the conductive bumps and covers the conductive bumps. Additionally, a manufacturing method of the chip packaging structure is also provided.
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