METHOD FOR FABRICATING A QUASI-SOI SOURCE-DRAIN MULTI-GATE DEVICE
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United States of America Patent
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app pub date -
Mar 31, 2014
filing date -
Dec 18, 2013
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Abstract
The present invention discloses a method for fabricating a quasi SOI source-drain multi-gate device, belonging to a field of manufacturing ultra large scale integrated circuit, the method comprises in sequence the following steps of: forming a Fin strip-shaped active region on a first semiconductor substrate; forming a STI isolation layer; depositing a gate dielectric layer and a gate material layer, forming a gate stack structure; forming a doped structure of a source-drain extension region; forming a recessed source-drain structure; forming a quasi SOI source-drain isolation layer; in-situ doping an epitaxial source and drain of a second semiconductor material and performing annealing for activating; removing a dummy gate and performing a deposition of a high k metal gate again; and forming a contact and a metal interconnection.
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