Additive Fabrication of Single and Multi-Layer Electronic Circuits
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United States of America Patent
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Aug 18, 2016
app pub date -
Feb 18, 2016
filing date -
Feb 18, 2015
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A method and apparatus for the additive fabrication of single and multi-layer electronic circuits by using directed local deposition of conductive, insulating, and/or dielectric materials to build circuit layers incorporating conductive, insulating and/or dielectric features, including inter-layer vias and embedded electronic components. Different conductive, insulating, and/or dielectric materials can be deposited at different points in the circuit such that any section of the circuit may be tailored for specific electrical, thermal, or mechanical properties. This enables more geometric and spatial flexibility in electronic circuit implementation, which optimizes the use of space such that more compact circuits can be manufactured.
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