CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Aug 18, 2016
app pub date -
Jan 26, 2016
filing date -
Feb 16, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection layer. The dielectric bonding layer is located on the protection layer and between the carrier and the protection layer. The carrier, the dielectric bonding layer, and the protection layer have a communicated through hole configured to expose the conductive pad. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the conductive pad, the sidewall of the through hole, and a surface of the carrier facing away from the dielectric bonding layer. The passive component portion is located on the surface of the carrier, and an end of the passive component portion is connected to the connection portion that is on the surface of the carrier.
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