FIELD EFFECT TRANSISTOR ARRANGEMENT
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United States of America Patent
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app pub date -
Jun 25, 2014
filing date -
Jun 26, 2013
priority date (Note) -
Abandoned
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Abstract
A field effect transistor arrangement having as planar channel layer comprises semiconductor material, the whole surface of the underside of the layer being applied to an upper side of an electrically insulating substrate layer and the upper side of the planar channel layer being covered by an insulation layer. The arrangement has a source electrode on a first side edge of the channel layer and a drain electrode on a second side edge of the channel layer and a control electrode arranged above the channel layer. An adjusting electrode is arranged on an underside of the substrate layer. A contact region between the source and drain electrodes and the planar channel layer is in each case configured as a midgap Schottky barrier. A respective barrier control electrode is arranged in the vicinity of the contact region of the source electrode and of the drain electrode, Each barrier control electrode can have a section that projects outwards in the direction of the planar channel layer.
First Claim
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Family
| Country | kind | publication No. | Filing Date |
|---|---|---|---|
| DE | A1 | DE102013106729 | Jun 26, 2013 |
| WO | A1 | WO2014207078 | Jun 25, 2014 |
| EP | B1 | EP3014658 | Jun 25, 2014 |
| US | A1 | US20180076323 | Nov 10, 2017 |
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