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United States of America Patent

APP PUB NO 20160216327A1
SERIAL NO

15026585

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Abstract

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A system and method are provided on one or more companion chips having a plurality of cores. Each core has core circuitry and a test interface for carrying out tests in relation to the core circuitry. The test interface has an address register to hold an address of the core and address determination circuitry. The address determination circuitry is configured to compare an address received on an address line to the address held in the address register to determine whether a core is being addressed. The address determination circuitry is also configured to direct the test interface to carry out a testing operation in response to the determination.

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Patent Owner(s)

Patent OwnerAddress
STMICROELECTRONICS (RESEARCH AND DEVELOPMENT) LIMITEDPLANAR HOUSE PARKWAY GLOBE PARK MARLOW BUCKINGHAMSHIRE SL7 1YL

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
FIRTH, Stephen Chepstow, GB 3 2
NAPOLITANO, Leonardo Bristol, GB 3 7

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  • 2 Citation Count
  • G06F Class
  • 11.69 % this patent is cited more than
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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3122144564193188710466053822701961379632401 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +010002000300040005000600070008000900010000110001200013000140001500016000

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