TRANSISTOR TESTING CIRCUIT AND METHOD THEREOF, SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR APPARATUS
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United States of America Patent
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Issued Date -
Jul 28, 2016
app pub date -
Jun 17, 2015
filing date -
Jun 17, 2015
priority date (Note) -
Published
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Abstract
A transistor testing circuit for measuring a breakdown voltage of a transistor included in a semiconductor apparatus with high accuracy for each chip is provided. The transistor testing circuit is disposed on a semiconductor chip to measure the breakdown voltage of a MOS transistor. The transistor testing circuit includes: a voltage applying apparatus, a current detecting circuit, a current mirror voltage outputting circuit, and a comparator circuit. The voltage applying apparatus applies a predetermined testing voltage to at least one of a drain, a source, and a gate of the MOS transistor. When the testing voltage is applied, the current detecting circuit detects a current flowing from the MOS transistor to a load circuit. The current mirror voltage outputting circuit generates a mirror current corresponding to the detected current and outputs the same. The comparator circuit compares the mirror current with a predetermined reference current to output a comparison result signal.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
POWERCHIP TECHNOLOGY CORPORATION | NO 12 LI-HSIN RD I SCIENCE-BASED INDUSTRIAL PARK HSINCHU |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Ogawa, Akira | Tokyo, JP | 126 | 2141 |
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jan 28, 2028 |
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Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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