TEST DEVICE FOR ELIMINATING ELECTROSTATIC CHARGES
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United States of America Patent
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Issued Date -
Jul 21, 2016
app pub date -
Jan 15, 2015
filing date -
Jan 15, 2015
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Abstract
In a test device for eliminating electrostatic charges, an elimination integrated circuit (IC) has a plurality of first pins, a second pin and a third pin. The first pins are respectively connected with a plurality of fourth pins of at least one tested integrated circuit (IC), and electrostatic charges are on a surface of the tested IC. The third pin is connected with ground. The fourth pins respectively contact a plurality of probes of a tester. The second pin receives a turn-on signal, the elimination IC uses the turn-on signal to form conduction paths between the tested IC and ground and to discharge the electrostatic charges to ground through the first pins and the third pin. Then, the second pin receives a turn-off signal, the elimination IC uses the turn-off signal to cut off the conduction paths and the tester tests the tested IC.
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