SYSTEM ON CHIP CAPABLE OF BEING DEBUGGED IN ABNORMAL OPERATING STATE AND DEBUGGING METHOD FOR SYSTEM ON CHIP
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United States of America Patent
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Issued Date -
Jul 14, 2016
app pub date -
Mar 12, 2015
filing date -
Jan 14, 2015
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Abstract
A system on chip capable of being debugged in an abnormal operation state and a debugging method for system on chip are provided. A switch unit is connected to a function module through a first path and is connected to a test connection interface of a processor through a second path. A pin unit is connected to the switch unit through a third path. A control module receives input data, outputs a selection signal to the switch unit, and determines the level of the selection signal according to the input data. The switch unit selects to connect the third path to one of the first path and the second path according to the level of the selection signal. When the third path is connected to the second path, the debugging platform performs a debugging procedure on the processor via the test connection interface.
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