HYBRID WAFER DICING APPROACH USING A POLYGON SCANNING-BASED LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS
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United States of America Patent
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Issued Date -
Jul 7, 2016
app pub date -
Jan 5, 2015
filing date -
Jan 5, 2015
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Abstract
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the plurality of integrated circuits. The mask is then patterned with a polygon scanning-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the plurality of integrated circuits.
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