METHOD AND STRUCTURE FOR FAN-OUT WAFER LEVEL PACKAGING
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United States of America Patent
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Jun 30, 2016
app pub date -
Dec 21, 2015
filing date -
Dec 24, 2014
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Abstract
A method for fan-out wafer level packaging includes: providing a carrier substrate; forming a strippable protective film with a polarity of openings; forming at least one metal layer in the openings; removing the carrier substrate; mounting a plurality of chips onto the metal layer and electrically connecting the chips to the metal layer; packing the chips, the metal layer, and the strippable protective film by using a packaging layer; forming a plurality of redistribution layers; and finally, forming soldering balls on the surfaces of the redistribution layers.
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