METHOD AND STRUCTURE FOR FAN-OUT WAFER LEVEL PACKAGING
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United States of America Patent
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Jun 30, 2016
app pub date -
Dec 21, 2015
filing date -
Dec 24, 2014
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Abstract
A method for fan-out wafer level chip packaging includes: providing a carrier substrate; forming a plurality of conductive base layers on a surface of the carrier substrate; mounting a plurality of chips on the conductive base layers and electrically connecting the chips to the conductive base layers by using a plurality of wire leads; forming a packaging layer to encapsulate the chips, the wire leads, the conductive base layers, and a top surface of the carrier substrate; removing the carrier substrate; and forming a plurality of conductive layers on bottom surfaces of the conductive base layers.
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