JFET DEVICE AND ITS MANUFACTURING METHOD
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United States of America Patent
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Issued Date -
Jun 23, 2016
app pub date -
Dec 23, 2014
filing date -
Dec 23, 2014
priority date (Note) -
Abandoned
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Abstract
The present invention discloses a JFET device, whose drift region is composed of a first deep well region doped with the second conduction type that is formed on a substrate doped with the first conduction type; the body region includes a second deep well region and channel region doped with the second conduction type; the channel region, located between the first deep well region and the second deep well region, includes two or more third deep well regions doped with the second conduction type that are arranged at equal intervals, with the doping impurities of the spacing region between the adjacent third deep well regions composed of the diffusion impurities of the adjacent third deep well regions; the processing conditions are the same for the three deep well regions. Regulating the pinch-off voltage of the JFET device by regulating the impurity concentration of the deep well region, and the width and number of the respective spacing regions. The present invention further discloses a method for manufacturing the JFET device. The present invention can reduce the pinch-off voltage, and regulate the pinch-off voltage conveniently, easy to meet the requirements for various pinch-off voltages.
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