Power FET Having Reduced Gate Resistance
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United States of America Patent
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app pub date -
Dec 1, 2015
filing date -
Dec 16, 2014
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Abstract
In one implementation, a power field-effect transistor (FET) having a reduced gate resistance includes a drain, a source, a gate, and a gate contact including a gate pad, a gate highway, and multiple gate buses. The gate buses are formed from a first metal layer having a first thickness, while the gate pad and the gate highway each include a metal stack including the first metal layer and a second metal layer. The second metal layer has a second thickness substantially greater than the first thickness, thereby reducing the gate resistance of the power FET.
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