SINGLE-CHIP INTEGRATED CIRCUIT WITH CAPACITIVE ISOLATION AND METHOD FOR MAKING THE SAME
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United States of America Patent
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Issued Date -
Jun 9, 2016
app pub date -
Feb 17, 2016
filing date -
Nov 18, 2010
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Abstract
An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.
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