ASYMMETRIC PROCESSOR WITH CORES THAT SUPPORT DIFFERENT ISA INSTRUCTION SUBSETS
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United States of America Patent
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Issued Date -
Jun 9, 2016
app pub date -
Dec 2, 2015
filing date -
Mar 26, 2013
priority date (Note) -
Abandoned
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Abstract
An asymmetric multi-core processor uses at least two asymmetric cores to collectively support the instructions of an instruction set architecture (ISA). A general-feature core and a special feature core that support different instruction subsets of the ISA. A switch manager detects whether a thread includes an instruction that is not supported by the currently-executing core and, after detecting such an instruction, switches the thread to the other core.
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