Process Skew Resilient Digital CMOS Circuit
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United States of America Patent
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Jun 9, 2016
app pub date -
Dec 4, 2015
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Dec 4, 2015
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Abstract
A digital CMOS circuit comprising at least one pull-up circuit arranged, when in an on-state, to switch an output node of the digital CMOS circuit from a first voltage level to a second voltage level within a rising transition delay. The digital CMOS circuit further comprises at least one pull-down circuit arranged, when in an on-state, to switch the voltage level of the output node of the digital CMOS circuit from the second voltage level to the first voltage level within a falling transition delay. The digital CMOS circuit further comprises at least one performance matching transistor serially connected to the first and second type transistors, the gate terminal of which is connected to biasing means arranged for biasing the at least one performance matching transistor in such a way so as to compensate for the performance mismatch between the at least one first and second type transistors.
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