ASYMMETRIC ULTRATHIN SOI MOS TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
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United States of America Patent
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Issued Date -
Jun 2, 2016
app pub date -
Oct 21, 2013
filing date -
Oct 14, 2013
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Abstract
A method for manufacturing an asymmetric super-thin SOIMOS transistor is disclosed. The method comprises: a. providing a substrate composed of an insulating layer (200) and a semiconductor layer (300); b. forming a gate stack (304) on the substrate; c. removing semiconductor materials of the semiconductor layer (300) on a source region side to form a first vacancy (001); d. removing insulating materials of the insulating layer (200) in the source region and under channel near the source region to form a second vacancy (002); e. filling semiconductor materials into the first vacancy (001) and the second vacancy (002) to connect with the semiconductor materials above the second vacancy (002); and f. performing source/drain implantation. Compared with the prior art, the method of the disclosure can suppress the short channel effects and enhance device performance.
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