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Abstract

A system and method are provided for controlling the power mode of operation of a memory device. The system includes a processing device for performing processing operations on data, and a memory controller associated with the memory device, the memory device being used to store data for access by the processing device. The memory controller has power mode control circuitry to switch the memory device between different power modes of operation. Further, an interrupt controller is configured to issue an event signal to the processing device to trigger performance of at least one processing operation. On issuing the event signal, the interrupt controller further initiates generation of a wakeup stimulus signal to the power mode control circuitry, and the power mode control circuitry is then arranged to determine whether to change the power mode of operation of the memory device in dependence on the wakeup stimulus signal. By such an approach, the wakeup stimulus signal can provide an early trigger to the power mode control circuitry to exit the memory device from at least one low power mode of operation in anticipation of the performance of the at least one processing operation by the processing device requiring data to be accessed in the memory device.

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First Claim