Turbo decoders with stored column indexes for interleaver address generation and out-of-bounds detection and associated methods
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United States of America Patent
Stats
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Apr 23, 2019
Grant Date -
May 26, 2016
app pub date -
Nov 26, 2014
filing date -
Nov 26, 2014
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
NXP USA INC | 6501 WEST WILLIAM CANNON DRIVE AUSTIN TX 78735 |
International Classification(s)

- 2014 Application Filing Year
- H03M Class
- 1593 Applications Filed
- 1478 Patents Issued To-Date
- 92.79 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Bahary, Robert | Arlington Heights, US | 7 | 21 |
# of filed Patents : 7 Total Citations : 21 | |||
Jackowski, Eric J | Austin, US | 5 | 15 |
# of filed Patents : 5 Total Citations : 15 |
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- 1 Citation Count
- H03M Class
- 28.58 % this patent is cited more than
- 6 Age
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