MEMORY CELL ARRAY OF RESISTIVE RANDOM-ACCESS MEMORIES
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United States of America Patent
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Issued Date -
May 26, 2016
app pub date -
Oct 7, 2015
filing date -
Oct 7, 2015
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Abstract
A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line.
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