EFFICIENT IMPLEMENTATIONS FOR MAPREDUCE SYSTEMS

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United States of America Patent

APP PUB NO 20160132541A1
SERIAL NO

14821601

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Abstract

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Techniques for use with a processor configured to function as at least a Mapper in a MapReduce system include generating a set of [key, value] pairs by executing a Map function on input data. The set of [key, value] pairs may be stored in a storage system implemented on at least one data storage medium, the storage system being organized into a plurality of divisions with different divisions of the storage system storing [key, value] pairs corresponding to different keys. A first [key, value] pair corresponding to a first key handled by a first Reducer in the MapReduce system and a second [key, value] pair corresponding to a second key handled by a second Reducer in the MapReduce system may both be stored in a first division of the plurality of divisions.

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Patent Owner(s)

Patent OwnerAddress
COGNITIVE ELECTRONICS INCLEBANON NH

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Felch, Andrew C Palo Alto, US 26 647

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