Load transient, reduced bond wires for circuits supplying large currents
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United States of America Patent
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Sep 27, 2016
Grant Date -
May 12, 2016
app pub date -
Jan 15, 2016
filing date -
Oct 16, 2012
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Abstract
Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.
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