DEFECT REDUCTION METHODS AND COMPOSITION FOR VIA FORMATION IN DIRECTED SELF-ASSEMBLY PATTERNING

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United States of America Patent

APP PUB NO 20160122580A1
SERIAL NO

14527962

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Abstract

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The present invention relates to a two novel processes, “Dual Coating Process and Single Coating Process,” for forming an array of via's by employing a graphoepitaxy approach, where an array of pillars the surface of the pillars has been modified by the formation of a hydrophobic poly(vinyl aryl) brush at the surface of the pillars. The present invention also relates to a composition comprising a poly(vinyl aryl) hydrophopic polymer brush precursor terminated at one chain end with a reactive functional group, a diblock copolymer comprising an etch resistant hydrophobic block and a highly etchable hydrophilic block, a thermal acid generator and a solvent.

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Patent Owner(s)

Patent OwnerAddress
AZ ELECTRONIC MATERIALS (LUXEMBOURG) S A R L32-36 BOULEVARD D'AVRANCHES LUXEMBOURG L-1160

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
AKIYAMA, Yasushi Shizuoka, JP 13 26
HONG, SungEun Basking Ridge, US 11 239
KUROSAWA, Kazunori Shizuoka, JP 10 32
LIN, Guanyang Whitehouse Station, US 30 421
MATSUMOTO, Naoki Shizuoka, JP 303 9159
MIYAZAKI, Shinji Shizuoka, JP 62 1159

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