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Abstract

A diagnostic apparatus is disclosed, which includes a processor configured to extract, from a plurality of components included in an integrated circuit to be diagnosed, a failure candidate based on test results obtained from actual operations of the integrated circuit, the actual operations being implemented by individually applying a plurality of types of test patterns to the integrated circuit, extract, from a plurality of pass patterns of the test patterns, a pass pattern with which a signal is transmitted to the failure candidate, based on log data obtained from simulations with the test patterns, the test results of the plurality of pass patterns being normal, and execute, using a fail pattern of the test patterns and the extracted pass patterns, a failure simulation assuming that the failure candidate is failed, the test result of the fail pattern being abnormal.

First Claim