SYSTEM AND METHOD FOR ELIMINATING INDETERMINISM IN INTEGRATED CIRCUIT TESTING
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United States of America Patent
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Issued Date -
Apr 21, 2016
app pub date -
Oct 16, 2014
filing date -
Oct 16, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
Indeterministic launch of test transactions in a system-on-chip device having asynchronous paths may be avoided by gating test mode bus transactions at the functional (IP) module interface. The gated bus transactions are released using an external trigger in order to control loss of cycle accuracy caused by on-board synchronizers during functional testing. Conventional interfaces can be driven from automatic test equipment and controlled in order to account for PVT variations and achieve deterministic and stable behavior of the device while being tested.
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