PASSIVE ANALOG SAMPLE AND HOLD IN ANALOG-TO-DIGITAL CONVERTERS
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United States of America Patent
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Issued Date -
Apr 14, 2016
app pub date -
Oct 10, 2014
filing date -
Oct 10, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.
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