Robust and Reliable Power Semiconductor Package
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United States of America Patent
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Issued Date -
Apr 14, 2016
app pub date -
Sep 22, 2015
filing date -
Oct 9, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
In one implementation, a semiconductor package includes a patterned conductive carrier including a support segment having a partially etched recess. The semiconductor package also includes an integrated circuit (IC) situated on the support segment, and an electrical connector coupling the IC to the partially etched recess. In addition, the semiconductor package includes a packaging dielectric formed over the patterned conductive carrier and the IC. The packaging dielectric interfaces with and mechanically engages the partially etched recess so as to prevent delamination of the electrical connector.
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