METHOD AND SYSTEM FOR EXTENDING DIE SIZE AND PACKAGED SEMICONDUCTOR DEVICES INCORPORATING THE SAME
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United States of America Patent
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Issued Date -
Apr 14, 2016
app pub date -
Oct 8, 2014
filing date -
Oct 8, 2014
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Abstract
A packaged semiconductor device includes a die flag and a plurality of lead frame fingers each having a proximate end spaced apart from the die flag. A first surface of a spacer mechanically and electrically couples to a first surface of the die flag, and a first surface of a die mechanically and electrically couples to a second surface of the spacer. At least one electrical connector electrically couples an electrical contact on a second surface of the die with a lead frame finger. A molding compound encapsulates the die, spacer, at least a portion of the at least one electrical connector, at least a portion of the die flag, and at least a portion of each lead frame finger. A width of the spacer along the second surface of the spacer is greater than a width of the die flag along the first surface of the die flag.
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