METHODS FOR ETCHING A BARRIER LAYER FOR AN INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR APPLICATIONS
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United States of America Patent
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Issued Date -
Apr 7, 2016
app pub date -
Oct 3, 2014
filing date -
Oct 3, 2014
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Abandoned
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Abstract
Embodiments of the present disclosure provide methods for etching a barrier layer disposed under a metal layer, such as a copper layer, when the metal layer is etched open exposing the barrier layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of etching a barrier layer disposed under a metal layer formed on a substrate includes supplying a first etching gas mixture comprising a hydrogen containing gas and an inert gas into a processing chamber to clean a surface of a barrier layer disposed on a substrate for a first period of time, supplying a second etching gas mixture comprising fluorine containing gas into the processing chamber to etch the barrier layer, and switching to supply the first etching gas in the processing chamber to clean the etched barrier layer for a second period of time.
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