COLUMN DECODER CIRCUITRY FOR A NON-VOLATILE MEMORY
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United States of America Patent
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Issued Date -
Apr 7, 2016
app pub date -
Oct 6, 2014
filing date -
Oct 6, 2014
priority date (Note) -
Abandoned
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Abstract
A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating.
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