DUAL STAGE SENSING CURRENT WITH REDUCED PULSE WIDTH FOR READING RESISTIVE MEMORY
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United States of America Patent
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Issued Date -
Mar 31, 2016
app pub date -
Sep 27, 2014
filing date -
Sep 27, 2014
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Abandoned
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Abstract
Systems and methods for reducing a probability of read disturbance during a read operation on a resistive memory bit cell include a dual stage sensing scheme, which is used to reduce pulse widths of sensing currents for reading the resistive memory bit cell. During a first stage of the read operation on the resistive memory bit cell, a first sensing current is passed in a first direction through the resistive memory bit cell, and during a second stage of the read operation, a second sensing current is passed in an opposite, second direction through the resistive memory bit cell. Durations of the first and second stages are each equal to half of the duration of the read operation, which reduces pulse width of the first and second sensing currents. Probability of read disturbance occurring is limited to at most one of the first or second stages.
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