Importance

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Abstract

A transmitter and receiver circuit includes a phase interpolator that generates a process clock having a phase based on a reference clock, a first selector that selects a first clock so that the first clock is the process clock in a first mode and is the reference clock in a second mode, a deserializer that converts a serial input data into a parallel output data in accordance with the first clock and outputs the parallel output data, a second selector that selects a second clock so that the second clock is the reference clock in the first mode and is the process clock in the second mode, and a serializer that converts a second parallel input data into a serial output data according to the second clock and outputs the serial output data.

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First Claim