SOLID STATE STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF
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United States of America Patent
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Issued Date -
Mar 17, 2016
app pub date -
Mar 11, 2015
filing date -
Sep 12, 2014
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Abandoned
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Abstract
An error correction method for a solid state storage device is provided. A controller of the solid state storage device issues plural slicing voltages to a flash memory. The flash memory issues a soft data to a soft decoder of the controller according to the plural slicing voltages. Firstly, the soft decoder receives the soft data, and performs an error correction process of the soft data according to a predetermined log-likelihood ratio (LLR) parameter set. If the error correction process of the soft data is not successfully completed according to the predetermined LLR parameter set, one LLR parameter set is selected from plural parameter sets of a LLR table and the error correction process of the soft data is performed according to the selected LLR parameter set.
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