Layer Electrode For Touchscreen
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United States of America Patent
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Issued Date -
Mar 17, 2016
app pub date -
May 6, 2014
filing date -
May 6, 2013
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Abstract
The invention relates to a layer electrode for a touchscreen, in particular one which makes the edge region of the transparent input field matrix useful for further input fields.
First Claim
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Country | kind | publication No. | Filing Date | Type | Sub-Type |
---|---|---|---|---|---|
DE | A1 | DE102013104640 | May 06, 2013 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
DOC. LAID OPEN (FIRST PUBLICATION) | Schichtelektrode für Berührungsbildschirm | Nov 06, 2014 | |||
CN | A | CN105229577 | May 06, 2014 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
UNEXAMINED APPLICATION FOR A PATENT FOR INV. | For the layer electrode of touch-screen | Jan 06, 2016 | |||
KR | A | KR20160004294 | May 06, 2014 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
UNEXAMINED PATENT APPLICATION | 터치스크린을 위한 층 전극 | Jan 12, 2016 | |||
WO | A1 | WO2014180831 | May 06, 2014 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
INTERNATIONAL APPLICATION PUBLISHED WITH INTERNATIONAL SEARCH REPORT | SCHICHTELEKTRODE FÜR BERÜHRUNGSBILDSCHIRM | Nov 13, 2014 |
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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POLYIC GMBH & CO KG | PAUL-GOSSEN-STRASSE 100 ERLANGEN 91052 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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ULLMANN, Andreas | Zirndorf, DE | 49 | 248 |
# of filed Patents : 49 Total Citations : 248 | |||
WALTER, Manfred | Nurnberg, DE | 74 | 637 |
# of filed Patents : 74 Total Citations : 637 |
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Patent Citation Ranking
- 4 Citation Count
- G06F Class
- 11.69 % this patent is cited more than
- 9 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
---|---|---|---|---|
11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Sep 17, 2027 |
Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
US Patent Application No: 2018/0156,749
COMPUTER IMPLEMENTED METHOD FOR DETERMINING INTRINSIC PARAMETER IN A STACKED NANOWIRES MOSFET
Abstract
Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:
- measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets Nw,width Ww,i, of the nanowire/nanosheet number i, i being an integer from 1 to Nw,thickness of the nanowire/nanosheet Hw,i, number i, i being an integer from 1 to Nw,corner radius Rw,i of the nanowire/nanosheet number i, i being an integer from 1 to Nw, Rw,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ΦT given by ΦT=kBT/q;measuring the total gate capacitance for a plurality of gate voltages;determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowires/nanosheets MOSFET.
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