SYSTEM FOR TESTING IC DESIGN
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United States of America Patent
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Issued Date -
Mar 10, 2016
app pub date -
Sep 9, 2014
filing date -
Sep 9, 2014
priority date (Note) -
Abandoned
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Abstract
A method for testing an integrated circuit design exercises the design using a set of simulation signals, and partitions a representation of the design into a first set of active elements and a second set of inactive elements. Only the active elements of the first set are exercised using a second set of simulation signals during verification of the integrated circuit design.
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