Flip-flop for reducing dynamic power
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United States of America Patent
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Aug 22, 2017
Grant Date -
Feb 25, 2016
app pub date -
May 8, 2013
filing date -
May 8, 2013
priority date (Note) -
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Abstract
A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.
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