STAPLING eIF4E INTERACTING PEPTIDES
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United States of America Patent
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Issued Date -
Feb 18, 2016
app pub date -
Feb 28, 2014
filing date -
Mar 21, 2013
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Abstract
The present invention relates to cross-linked peptides that are associated with human eIF4G and bind to eIF4E, uses thereof and pharmaceutical compositions comprising the peptides.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH | SINGAPORE SINGAPORE |
International Classification(s)

- 2014 Application Filing Year
- C07K Class
- 4412 Applications Filed
- 3459 Patents Issued To-Date
- 78.40 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Brown, Christopher John | Singapore, SG | 47 | 210 |
# of filed Patents : 47 Total Citations : 210 | |||
Lama, Dilraj | Singapore, SG | 1 | 1 |
# of filed Patents : 1 Total Citations : 1 | |||
Lane, David Philip | Singapore, SG | 21 | 313 |
# of filed Patents : 21 Total Citations : 313 | |||
Quah, Soo Tng | Singapore, SG | 1 | 1 |
# of filed Patents : 1 Total Citations : 1 | |||
Verma, Chandra Shekhar | Singapore, SG | 13 | 8 |
# of filed Patents : 13 Total Citations : 8 |
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Patent Citation Ranking
- 1 Citation Count
- C07K Class
- 52.71 % this patent is cited more than
- 9 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
---|---|---|---|---|
11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Aug 18, 2027 |
Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
US Patent Application No: 2008/0030,231
Level Shifter and Voltage Converting Device
Abstract
A level shifter voltage contributing to a simplified interface and realizing a reduced power consumption and a voltage supplying device using such a level shifter are provided. A level shifter (1) receives an input data (Din) having a voltage of 0V (zero) and a clock signal (CLK) to shift said voltage of 0V to 5V. The level shifter (1) comprises a first means for supplying a voltage of Vdd(=5V) to a node (N1) and a second means for supplying a voltage of Vss(=0V) to the node (N1). The second means operates so as to block a supply of the voltage of Vss to the node (N1) when the first means supplies the voltage of Vdd to the node (N1).
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