Importance

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Abstract

Embodiments disclosed pertain to apparatuses, systems, and methods for fast integer division. Disclosed embodiments pertain to an integer divide circuit to divide a dividend by a divisor and produce multiple quotient bits per iteration. In some embodiments, the fast integer divider may include a partial remainder register initialized with the dividend. Further, the fast integer divider circuit may include a plurality of adders, where each adder subtracts a multiple of the divisor from the current value in the partial remainder register. A logic block coupled to each of the adders, determines multiple quotient bits at each iteration based on the subtraction results.

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First Claim