Method of semiconductor integrated circuit fabrication
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United States of America Patent
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Jun 2, 2020
Grant Date -
Jan 28, 2016
app pub date -
Oct 5, 2015
filing date -
Oct 30, 2013
priority date (Note) -
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Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
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