Method of semiconductor integrated circuit fabrication
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 2, 2020
Grant Date -
Jan 28, 2016
app pub date -
Oct 5, 2015
filing date -
Oct 30, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
|
US Family Size
|
Non-US Coverage
|
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
First Claim
Other Claims data not available
Family
| Country | kind | publication No. | Filing Date | Type | Sub-Type |
|---|
International Classification(s)
- 2015 Application Filing Year
- H01L Class
- 25498 Applications Filed
- 22451 Patents Issued To-Date
- 88.06 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 2 Citation Count
- H01L Class
- 41.95 % this patent is cited more than
- 5 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Dec 2, 2027 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Dec 2, 2031 |
