LAMINATED HIGH BIAS RETENTION FERRITE SUPPRESSORS AND METHODS OF MAKING THE SAME
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United States of America Patent
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Sep 10, 2015
filing date -
Mar 15, 2013
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Abstract
Disclosed are exemplary embodiments of chip type high bias retention suppressors that have a laminated structure, which comprises a ferrite magnetic substrate, dielectric material layers, and interior electrically-conductive or conductor layers. The internal electrical conductors may be printed (e.g., silver ink, etc.) on the magnetic layers such that the conductors connect with each other and define a spiral pattern or coil. The dielectric layers and/or interior conductors may be laminated on the magnetic substrate in a direction of thickness. The dielectric layers and/or interior connectors may be printed by a thick-film process.
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