Circuit for canceling errors caused by parasitic and device-intrinsic resistances in temperature dependent integrated circuits
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United States of America Patent
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Dec 27, 2016
Grant Date -
Dec 24, 2015
app pub date -
Feb 5, 2014
filing date -
Feb 15, 2013
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Abstract
In one embodiment, a circuit includes at least one transistor with a base and collector being electrically connected to a ground, and at least one current source being configured to apply four different currents (A, B, C, and D) to the emitter. A sum of the currents A and C are substantially equivalent to a sum of the currents B and D, or a sum of the currents A and D are substantially equivalent to a sum of the currents B and C. The circuit outputs first, second, third, and fourth voltage potentials between the emitter and the base during application of the currents A, B, C, and D, respectively.
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