VARIABLE SELECTIVITY SILICON GROWTH PROCESS
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Dec 24, 2015
app pub date -
Jun 18, 2015
filing date -
Jun 20, 2014
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
The present invention is a means and a method for speeding up the fabrication process, lowering the cost and improving yields. The present invention is a method for manufacturing memory cells in a diode memory array by utilizing selective epitaxial growth techniques to form high quality silicon for diodes and then lesser quality silicon to fill recesses and prepare the surface for subsequent planarization or etching steps.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully