SOI WITH GOLD-DOPED HANDLE WAFER
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United States of America Patent
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Issued Date -
Dec 24, 2015
app pub date -
Jun 22, 2015
filing date -
Jun 20, 2014
priority date (Note) -
Abandoned
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Abstract
A method for manufacturing a semiconductor die includes providing an SOI semiconductor wafer including a substrate, an insulating layer over the substrate, and a device layer over the insulating layer. A surface of the SOI semiconductor wafer opposite the substrate is mounted to a temporary carrier mount, and the substrate is removed, leaving an exposed surface of the insulating layer. A high-resistivity gold-doped silicon substrate is then provided on the exposed surface of the insulating layer. By providing the high-resistivity gold-doped silicon substrate, an exceptionally high-resistivity substrate can be achieved, thereby minimizing field-dependent electrical interaction between the substrate and one or more semiconductor devices thereon. Accordingly, harmonic distortion in the semiconductor devices caused by the substrate will be reduced, thereby increasing the performance of the device.
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