TRIGGER DETECTION FOR POST CONFIGURATION TESTING OF PROGRAMMABLE LOGIC DEVICES
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
Dec 24, 2015
app pub date -
Jun 24, 2014
filing date -
Jun 24, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Various techniques are provided to determine signal values of a programmable logic device (PLD) prior to the running of an external test application. In one example, a machine-implemented method includes monitoring, by a PLD, a signal of the PLD. The method also includes detecting a trigger condition associated with the signal. The method also includes storing data in memory of the PLD corresponding to values of the signal. The method also includes passing the stored data from the PLD to an external device running a test application. The stored data comprises values of the signal occurring before the running of the test application.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
LATTICE SEMICONDUCTOR CORPORATION | 5555 N E MOORE CT HILLSBORO OR 97124-6421 |
International Classification(s)

- 2014 Application Filing Year
- G06F Class
- 51669 Applications Filed
- 44228 Patents Issued To-Date
- 85.60 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Caslis, Brian | Wilsonville, US | 1 | 1 |
# of filed Patents : 1 Total Citations : 1 | |||
Lenka, Pradeep | Milpitas, US | 3 | 6 |
# of filed Patents : 3 Total Citations : 6 | |||
Lin, Andrew | San Jose, US | 93 | 2621 |
# of filed Patents : 93 Total Citations : 2621 |
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Patent Citation Ranking
- 1 Citation Count
- G06F Class
- 8.54 % this patent is cited more than
- 10 Age
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jun 24, 2027 |
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