TRIGGER DETECTION FOR POST CONFIGURATION TESTING OF PROGRAMMABLE LOGIC DEVICES

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United States of America Patent

APP PUB NO 20150370672A1
SERIAL NO

14313443

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Various techniques are provided to determine signal values of a programmable logic device (PLD) prior to the running of an external test application. In one example, a machine-implemented method includes monitoring, by a PLD, a signal of the PLD. The method also includes detecting a trigger condition associated with the signal. The method also includes storing data in memory of the PLD corresponding to values of the signal. The method also includes passing the stored data from the PLD to an external device running a test application. The stored data comprises values of the signal occurring before the running of the test application.

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Patent Owner(s)

Patent OwnerAddress
LATTICE SEMICONDUCTOR CORPORATION5555 N E MOORE CT HILLSBORO OR 97124-6421

International Classification(s)

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  • 2014 Application Filing Year
  • G06F Class
  • 51669 Applications Filed
  • 44228 Patents Issued To-Date
  • 85.60 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2014201520162017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caslis, Brian Wilsonville, US 1 1
Lenka, Pradeep Milpitas, US 3 6
Lin, Andrew San Jose, US 93 2621

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  • 1 Citation Count
  • G06F Class
  • 8.54 % this patent is cited more than
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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges20301168241032130125571353233025016611746601 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +010002000300040005000600070008000900010000110001200013000

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