PACKAGE STRUCTURE
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United States of America Patent
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N/A
Issued Date -
Dec 17, 2015
app pub date -
Mar 19, 2015
filing date -
Jun 13, 2014
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A package structure includes a chip, a selective-electroplating epoxy compound, a patterned circuit layer and a plurality of conductive vias. The chip includes a plurality of solder pads, an active surface and a back surface opposite to the active surface. The solder pads are disposed on the active surface. The selective-electroplating epoxy compound covers the chip and includes non-conductive metal complex. The patterned circuit layer is disposed directly on a surface of the selective-electroplating epoxy compound. The conductive vias are disposed directly at the selective-electroplating epoxy compound to electrically connect the solder pads and the patterned circuit layer.
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